dimanche 8 juin 2014
Bagman (STERN - Valadon automation) source code released
VHDL source code for DE1, DE2 and DE0 Nano available at https://sourceforge.net/projects/darfpga
mardi 3 juin 2014
samedi 8 mars 2014
FPGA64 for DE0 nano, DE1 and DE2 source code not available
Source code for the FPGA64 for Terasic board DE0 nano, DE1 and DE2 are not available at the moment.
mercredi 5 mars 2014
C64 IEC interface schematics for DE0 nano, DE1 or DE2 board
IEC interface components :
- 1 TTL 74LS06 six open collector buffer inverter
- 6 resistors 2 kOhms
Gpio side :
- connect to gpio_0 for DE0 Nano
- connect to gpio_1 for DE1 or DE2
IEC side :
- to IEC/SD board
- to 1541 drive din connectors (+5V not connected )
FPGA64 for DE0 Nano, DE1, DE2-35
Keyboard main keys :
- F11 toggle joystick emulation port A or port B on numeric keypad.
- F12 toggle PAL / NTSC (some VGA monitor doesn't synched at 50Hz )
- key0 reset cpu
- gpio_1_in0 toggle PAL / NTSC mode at startup (use F12 after startup)
- gpio_1_in1 toggle15KHz (RBG SCART) / 31KHz (VGA)
- key0 reset cpu
- sw6 toggle PAL / NTSC mode at startup (use F12 after startup)
- sw9 toggle 15KHz (RBG SCART) / 31KHz (VGA)
- key0 reset cpu
- sw1 toggle PAL / NTSC mode at startup (use F12 after startup)
- sw0 toggle 15KHz (RBG SCART) / 31KHz (VGA)
- /FB load file browser from IEC drive
- run
- @cd< goes out of D64 (< is the left arrow symbol not the 'less than' symbol)
- @cd/ goes up one dir level
- @cd// goes to root dir
New PCB for DE0 nano : low cost Multi I/O
On the PCB
- Video DAC : RGB 3x4 bits, Hsync, Vsync ready for VGA 31KHz or RGB SCART 15KHz, 50/60Hz.
- Audio DAC : PWM stereo.
- PS2 protocol (on PS2 plug or USB plug )
- micro SD card socket
- 2 inputs and 10 input/output with protection diodes (5v tolerant)
- 20€ pcb alone (no components)
- 35€ with surface mount components and sd socket (no connectors)
mardi 14 janvier 2014
Hardware for DE0 Nano / DE2 board
On the breadboard :
- Video DAC : RGB 3x3 bits, Hsync, Vsync ready for VGA 31KHz or RGB SCART 15KHz, 50/60Hz.
- Audio DAC : PWM stereo.
- PS2 input only
- SRAM + IEC interface
SRAM + IEC interface for DE0 Nano or DE2 GPIO
- SRAM 512Kx8, 10/12ns
- IEC interface 3 bits (data, clk, atn), 3.3/5.0v converter, usable with original drives (1541...) or with modern IEC/SD replacement.
- 20€ pcb only (no components)
- 30€ with surface mount components (no connectors)
uIEC/SD plugged in :
Full configuration with external wiring :
- SUBD 15 pin HD for video, VGA via standard cable, specific cable required for SCART
- Jack 3.5 stereo for audio
- USB for keyboard (use PS2 keyboard ONLY)
Bagman on DE0 Nano
Based on the Stern arcade PCB. This realisation uses the DE0 Nano board.
Some external hardware are needed :
The FPGA contains 1 Z80, 1 AY3-8910 (sound) + 1 TMS5110 (speech synthetizer), 1 Tile generator and 8 sprites.
Standalone working from the embed EPCS.
Some external hardware are needed :
- Video DAC
- Audio DAC
- PS2 Keyboard input
The FPGA contains 1 Z80, 1 AY3-8910 (sound) + 1 TMS5110 (speech synthetizer), 1 Tile generator and 8 sprites.
Standalone working from the embed EPCS.
lundi 13 janvier 2014
Crazy Kong (FALCON) on DE0 Nano
Based on Falcon arcade PCB This realisation uses the DE0 Nano board.
Some external hardware needs to be added :
- SRAM
- Video DAC
- Audio DAC
- PS2 Keyboard input
Standalone working from the embed EPCS.
dimanche 5 janvier 2014
Commodore 64 on DE0 Nano
Based on the FPGA64 vhdl description from Peter Wendrich. This realisation uses the DE0 Nano board which has a large FPGA at low cost.
External hardware have to be added :
The IEC bus may be connected to a real commodore floppy drive (1541 ...) or to some replacement (µIEC/SD ...).
The FPGA contains 3 roms : KERNAL, BASIC and CHAR (Jiffydos kernal allow for speeding up the IEC bus) and a VHDL SID6581 emulation.
Standalone working from the embed EPCS.
External hardware have to be added :
- SRAM
- IEC interface
- Video DAC
- Audio DAC
- PS/2 keyboard input
The IEC bus may be connected to a real commodore floppy drive (1541 ...) or to some replacement (µIEC/SD ...).
The FPGA contains 3 roms : KERNAL, BASIC and CHAR (Jiffydos kernal allow for speeding up the IEC bus) and a VHDL SID6581 emulation.
Standalone working from the embed EPCS.
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